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7.3.1
Cready
This bit is set t o ‘1’ when the bit R ready changes state. This bit can also be written by the host.
7.3.2
CWProt
This bit is set to ‘ 1 ’ when the bit RWProt changes state. This bit can also be written by the host.
7.3.3
Rready
This bit is used to determine the internal state of the Ready signal. In I/O mode it is used as an interrupt request.
When written, this bit acts as a mask (Mready) for writing the corresponding bit Cready.
7.3.4
Wprot
This bit is always ‘0’ since the CompactFlash Memory Card does not have a Write Protect switch. Whe n written,
this bit acts as a mask for writing the corresponding CWProt bit.
7.3.5
Mready
This bit acts as a mask for writing the corresponding Cready bit.
7.3.6
MWProt
This bit when written acts as a mask for writing the corresponding CWProt bit.
Table 36: Pin Replacement Register (default value: 0Ch)
Operation
Read
Write
D7
0
0
D6
0
0
D5
Cready
Cready
D4
CWProt
CWProt
D3
1
0
D2
1
0
D1
Rready
Rready
D0
Wprot
MWProt
Table 37: Pin Replacement Changed Bit/Mask Bit Values
Initial Value of ‘C’ Status
Written by Host
‘C’ Bit ‘M’ Bit
Final ‘C’ Bit
Comments
0
1
X
X
X
X
0
1
0
0
1
1
0
1
0
1
Unchanged
Unchanged
Cleared by Host
Set by Host
7.4 Socket and Copy Register (206h in Attribute Memory)
This register contains additional configuration information which identifies the Card from other cards. This
register is always written by the system before writing the Configuration Option Register (see Table 38).
7.4.1 Drive #
This value can be used to address two different cards in the case of twin card configuration.
7.4.2 X
The socket number is ignored by the Card.
Table 38: Socket and Copy Register (default value: 00h)
Operation
Read
Write
D7
Reserved
0
D6
0
0
D5
0
0
D4
Drive #
Drive #
D3
0
X
D2
0
X
D1
0
X
D0
0
X
7.5 Attribute Memory Function
Attribute memory is a space where identification and configuration information are stored. Only 8 bit wide
accesses at even addresses can be performed in this area. The Card configuration registers are also located in the
Attribute Memory area, at base address 200h. Attribute memory is not accessible in True IDE mode of operation.
For the Attribute Memory Read function, signals – REG and – OE must be active and – WE inactive during the cycle.
As in the Main Memory Read functions, the signals – CE1 and – CE2 control the even and odd Byte address, but only
the even Byte data is valid during the Attribute Memory access. Refer to Table 39 for signal states and bus validity.
Table 39: Attribute Memor y Function
Function Mode
-REG
-CE2 (1)
-CE1 (1)
A10
A9
A0
-OE (1)
-WE (1)
D15 to D8
D7 to D0
Swissbit AG
Industriestrasse 4
Swissbit reserves the right to change products or specifications without notice.
Revision: 1.51
CH-9552 Bronschhofen
Switzerland
www.swissbit.com
industrial@swissbit.com
C-300_data_sheet_CF-HxBK_Rev151.doc
Page 48 of 99
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